View XR81411_8993723.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2014 exar corporation XR81411 universal quad clock - high frequency lvcmos/lvds/lvpecl clock synthesizer exar.com/XR81411 rev 1a 1 / 15 general description the XR81411 is a quad clock synthesizer with 4 independent plls in a compact lga-45 package. each synthesizer generates any frequency in the range of 10 mhz to 800mhz by utilizing a highly flexible delta sigma modulator and a wide ranging vco. the outputs are independently configu- rable for single ended lvcmos or diff erential lvds or lvpecl. the clock outputs have very low typical phase noise jitter of sub 0.6ps rms, while consuming extremely low power. the XR81411 uses a single reference and provides 4 independent outputs that can be configured as needed to sup- port a wide variety of applications. each of the XR81411s 4 independent plls include an integer/fractional divider, lvcmos/lvds/lvpecl output driver, 3.3v/2.5v supply, and gener- ates one of four selectable output frequencies from a single reference. the XR81411 is optimized for use with a fundamental mode 10mhz to 60mhz crystal (or system clock) and generates a selection of output frequencies ranging from 10mhz to 800mhz in either integer or fractional mode. in frac- tional mode, frequency resolution of better than 2hz steps can be achieved. the application diagram below shows a typical lan synthesizer configura- tion with any standard crystal o scillating in fundamental mode. the typical phase noise plot below shows the jitter integrated over the 12khz to 20mhz range that is widely used in these systems. features ? small footprint 5mm x 5mm lga package ? configurable outputs - as differential lvpecl/ lvds pair or as a single ended lvcmos. ? crystal oscillator interface which can also be overdriven using a singl e-ended reference clock ? output frequency range: 10mhz - 800mhz ? crystal/input fr equency: 10mhz to 60mhz, paral- lel resonant crystal ? vco range: 2ghz - 3ghz ? phase jitter @ - 125mhz (12khz - 20mhz): <0. 6ps rms - 125mhz (1.875mhz -20mhz): <0.25ps rms ? 3.3v or 2.5v operating supply ? -40c to 85c ambient operating temperature ? lead-free (rohs 6) package applications ? 10ge, ge lan/wan ? 2.5g/10g so net/sdh/otn ? xdsl, pcie ? low-jitter clock generation ? synchronized clock systems ordering information C last page typical application diagram and performance q1 q1 xt al_in xt al_ou t control pins q2 q2 q3 q3 q4 q4 XR81411 25mhz lvcmos * (10-200mhz) lvpecl * (10-800mhz) lvds * (10-800mhz) lvcmos * (10-200mhz) (* any frequency, any output format) -180 -160 -140 -120 -100 -80 -60 -40 -20 0 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 noise magnitude(dbc) offset frequency(hz) phase noise qs=125mhz cmos output q1=125mhz q2=125mhz q3=125mhz q4=125mhz
? 2014 exar corporation XR81411 2 / 15 exar.com/XR81411 rev 1a absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any maximum rating condition for extended periods may affect device reliability and lifetime. power supply voltage (v dd )....................................+4.2v input voltage......................................-0.5v to v dd + 0.5v output voltage...................................-0.5v to v dd + 0.5v reference frequency/input crystal........10mhz to 60mhz storage temperature...............................-55c to +125c lead temperature (soldering, 10 sec).....................300c esd rating (hbm - human body model).................2.0kv operating conditions operating temperature range.....................-40c to +85c electrical characteristics specifications are at t a = 25c, v dd = 3.3v5% or 2.5v5%, v l = v dd ; limits applying over the full -40c to +85c operat- ing temperature range are denoted by a ? . typical values represent the most likely parametric norm at t a = 25c, and are provided for reference purposes only. symbol parameter conditions min typ max units 3.3v power supply dc characteristics v dd power supply voltage ? 3.135 3.3 3.465 v i dd power supply current lvpecl lvds lvc m o s includes output loading measured at 800mhz, figure 5 , (note 1) measured at 800mhz, figure 8 , (note 1) measured at 200mhz, figure 10 , (note 1, 2) ? ? ? 385 165 140 415 19 0 170 ma ma ma 2.5v power supply dc characteristics v dd power supply voltage ? 2.375 2.5 2.625 v i dd power supply current lvpecl lvds lvc m o s includes output loading measured at 800mhz, figure 6 , ( n o t e 1 ) measured at 800mhz, figure 9 , ( n o t e 1 ) measured at 200mhz, figure 10 , (note 1, 2) ? ? ? 285 1 1 5 85 305 1 3 5 110 m a ma ma lvcmos/lvttl dc input characteristics v ih input high voltage (oe, fsel[1:0]) v dd = 3.465v ? 2.42 v dd + 0.3 v v dd = 2.625v ? 1.83 v dd + 0.3 v
? 2014 exar corporation XR81411 3 / 15 exar.com/XR81411 rev 1a * note 1: all outputs configured identically. * note 2: does not include the load current. v il input low voltage (oe, fsel[1:0]) v dd = 3.465v ? -0.3 1.03 v v dd = 2.625v ? -0.3 0.785 v i ih input high current (oe, fsel[1:0]) v in = v dd = 3.465v or 2.625v ? 15 a i il input low current (oe, fsel[1:0]) v in = 0v, v dd = 3.465v or 2.625v ? -10 a lvcmos dc output characteristics (v dd = 3.3 +/- 5% or v dd = 2.5 +/- 5%) v oh output high voltage output unloaded ? 0.8 * v dd v v ol output low voltage output unloaded ? 0.1 * v dd v lvpecl dc output characteristics (v dd = 3.3 +/- 5% or v dd = 2.5 +/- 5%) v oh output high voltage ? v dd - 1.3 v dd - 0.3 v v ol output low voltage ? v dd - 2.0 v dd - 1.6 v v swing peak-to-peak output voltage swing ? 0.6 1.2 v lvds dc output characteristics (v dd = 3.3 +/- 5% or v dd =2.5 +/- 5%) v od differential output voltage output < 1ghz ? 200 600 mv v oc common mode voltage ? 1.25 v crystal characteristics x mode mode of oscillations fundamental x f frequency 10 60 mhz esr equivalent series resistance 50 c s shunt capacitance 7pf ac characteristics f out output frequency 10 800 mhz t1 jit ( ? ) jitter gbe 125mhz (w/25mhz ref) integration range 12khz-20mhz 0.6 1.0 ps t2 jit ( ? ) jitter gbe 125mhz (w/25mhz ref) integration range 1.85mhz-20mhz 0.25 0.45 ps t3 jit ( ? ) jitter oc12 155.52mhz (w/19.44mhz ref) integration range 12khz-5mhz 0.7 ps t r /t f output rise/fall time 20% to 80%, see figure 12 ? 100 500 ps odc output duty cycle see figure 13 ? 45 55 % symbol parameter conditions min typ max units
? 2014 exar corporation XR81411 4 / 15 exar.com/XR81411 rev 1a pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 39 42 45 37 40 43 top view q1 q1 vdd1c xtal_in xtal_out fsel1_1 fsel0_1 nc oe_1 vdd1d q2 q2 vdd2 nc oe_2 vdd3 nc oe_3 fsel1_3 fsel0_3 vdd4d q4 q4 vdd4c oe_4 nc gnd pads 9, 18, 27, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 39 42 45 37 40 43 27 28 29 30 31 32 33 34 35 36 bottom view
? 2014 exar corporation XR81411 5 / 15 exar.com/XR81411 rev 1a pin assignments pin no. pin name type description 1 q1 output channel 1 positive clock output 2q1 output channel 1inverted clock output 3 vdd1c power channel 1 core supply voltage 4 xtal_in input crystal oscillator input. 5 xtal_out output crystal oscillator output (external reference input) 6 fsel1_4 input (900k ? pull-dwn) channel 4 output frequency select 1, msb (lvcmos/lvttl input). 7 fsel0_4 input (900k ? pull-dwn) channel 4 output frequency select 0, lsb (lvcmos/lvttl input). 8 nc no connection do not connect. 9 gnd gnd ground. 10 oe_4 input (900k ? pull-up) channel 4 output enable - lvcmos/lvttl active high input. outputs are enabled when oe = high. outputs are disabled when oe = low. 11 vdd4c power channel 4 core supply voltage. ) 12 q4 output channel 4 positive clock output. 13 q4 output channel 4 inverted clock output. 14 vdd4d power channel 4 driver supply voltage.) 15 fsel1_3 input (900k ? pull-dwn) channel 3 output frequency select 1, msb (lvcmos/lvttl input). 16 fsel0_3 input (900k ? pull-dwn) channel 3 output frequency select 0, lsb (lvcmos/lvttl input). 17 nc no connection do not connect. 18 gnd gnd ground. 19 oe_3 input (900k ? pull-up) channel 3 output enable - lvcmos/lvttl active high input. outputs are enabled when oe = high. outputs are disabled when oe = low. 20 vdd3 power channel 3 core and driver supply voltage. 21 q3 output channel 3 positive clock output. 22 q3 output channel 3 inverted output. 23 fsel1_2 input (900k ? pull-dwn) channel 2 output frequency select 1, msb (lvcmos/lvttl input). 24 fsel0_2 input (900k ? pull-dwn) channel 2 output frequency select 0, lsb (lvcmos/lvttl input). 25 nc no connection do not connect. 26 oe_2 input (900k ? pull-up) channel 2 output enable - lvcmos/lvttl active high input. outputs are enabled when oe = high. outputs are disabled when oe = low. 27 gnd gnd ground.
? 2014 exar corporation XR81411 6 / 15 exar.com/XR81411 rev 1a 28 vdd2 power channel 2 core and driver supply voltage. 29 q2 output channel 2 positive clock output. 30 q2 output channel 2 inverted clock output. 31 fsel1_1 input (900k ? pull-dwn) channel 1 output frequency select 1, msb (lvcmos/lvttl input). 32 fsel0_1 input (900k ? pull-dwn) channel 1 output frequency select 0, lsb (lvcmos/lvttl input). 33 nc no connection do not connect. 34 oe_1 input (900k ? pull-up) channel 1 output enable - lvcmos/lvttl active high input. outputs are enabled when oe = high. outputs are disabled when oe = low. 35 vdd1d power channel 1 driver supply voltage. pin no. pin name type description
? 2014 exar corporation XR81411 7 / 15 exar.com/XR81411 rev 1a functional block diagram pll1 pll4 pll2 pll3 osc xtal_in xtal_out oe_1 fsel0_1 fsel1_1 oe_2 fsel0_2 fsel1_2 oe_3 fsel0_3 fsel1_3 oe_4 fsel0_4 fsel1_4 c o n t r o l q1 q1 q2 q2 q3 q3 q4 q4 output driver 1 output driver 2 output driver 4 output driver 3 vdd1c vdd2 vdd3 vdd4c vdd1d vdd4d
? 2014 exar corporation XR81411 8 / 15 exar.com/XR81411 rev 1a typical performance characteristics figures 1, 2, 3 and 4 show typical phase noise performance pl ots for 125 mhz clock outputs on each of the four outputs. the data was taken using the industry standard agilent e5052b instrument. the integration range is the widely referenced 12khz to 20mhz range most often used in lan applications. figure 1: q1 - 125mhz oper ation, phase noise at 3.3v figure 2: q2 - 125mhz oper ation, phase noise at 3.3v)
? 2014 exar corporation XR81411 9 / 15 exar.com/XR81411 rev 1a figure 3: q3 - 125mhz oper ation, phase noise at 3.3v figure 4: q4 - 125mhz op eration, phase noise at 3.3v
? 2014 exar corporation XR81411 10 / 15 exar.com/XR81411 rev 1a application information termination for lvpecl outputs the termination schemes shown in figure 5 and figure 6 are typical for lvpecl outputs. matched impedance layout techniques should be used for the lvpecl output pairs to minimize any distortion that could impact your maximum operating frequency. figure 7 is an alternate termination scheme that uses a y-termination approach. figure 5: XR81411 3.3v lvpecl output termination figure 6: XR81411 2.5v lvpecl output termination figure 7: XR81411 alternate lvpecl output termination using y-termination termination for lvds outputs the termination schemes shown in figure 8 and figure 9 are typical for lvds outputs. lvds swing is a small, typi- cally 350mv, on 1.2v of common mode. the lvds output pair needs a 100 ? resistor across the differential pair as close to the destination as possible. figure 8: XR81411 3.3v lvds output termination figure 9: XR81411 2.5v lvds output termination termination for lvcmos outputs the termination scheme shown in figure 10 is typical for lvcmos outputs. a split supply approach can be used uti- lizing the scopes internal 50 ? impedance, as shown in figure 11. figure 10: XR81411 lvcmos output termination 3.3v 3.3v 3.3v 50 ? 50 ? 130 ? 130 ? 82 ? 82 ? lvpecl output lvpecl input 2.5v 2.5v 2.5v 50 ? 50 ? ???? ???? ????? ????? lvpecl output lvpecl input v dd v dd 50 ? 50 ? 50 ? 50 ? lvpecl output lvpecl input rtt for 3.3v systems rtt = 50 ? for 2.5v systems rtt = 19 ? 3.3v 3.3v 50 ? 50 ? 100 ? lvds output lvds input 2.5v 2.5v 50 ? 50 ? 100 ? lvds output lvds input 100 ? 100 ? z = 50 ? high impedance scope probe lvcmos output v dd v dd
? 2014 exar corporation XR81411 11 / 15 exar.com/XR81411 rev 1a figure 11: XR81411 split supply lvcmos output termination output signal timing definitions the following diagrams clarify the common definitions of the ac timing measurements. figure 12: output rise/fall time and swing figure 13: output period and duty cycle configurable attributes the XR81411 is highly adaptable and can be configured for many different applications. the device performance of the input stage, pll stages and the output stages can be adjusted (programmed by the factory) to meet any number of application requirements. input stage the XR81411s input is designed to be used with a parallel resonant crystal in the range of 10mhz to 60mhz. it can also be overdriven by an external single-ended source. the XR81411 uses a pierce oscillator circuit that has a vari- able gain control and selectable capacitor load options on each of the xtal pins. figure 14: XR81411 input stage the XR81411 input stage also has the ability to use a startup state that can configure the gain and capacitor load- ing conditions different from normal operation to improve crystal startup time. pll stages each of the independent plls within the XR81411 can be configured operate at any of four distinct settings. the pll takes the ref output from the input stage and can produce any frequency from 10mhz to 800mhz. the pll can be configured for integer or fractional operation. the internal calibration circuitry of the XR81411 will optimize the config- uration of the vco, lpf and divider (dsm, n and output) settings for the input and output frequencies chosen. figure 15: XR81411 pll ??? z = 50 ? lvcmos output +v dd /2 scope -v dd /2 vcc vss 20% 80% t r t f 80% 20% v swing q nq q nq t pw t period odc = x 100% t pw t period g xtal_in xtal_out c1 c2 XR81411 ref phase detector charge pump lowpass filter post divider n divider dsm ref control out?
? 2014 exar corporation XR81411 12 / 15 exar.com/XR81411 rev 1a each of the four universal clocks can support up to 4 indi- vidual output frequency configurations. once configured, the two frequency select pins, fslel[1:0], will determine the output frequency from the device. this allows the XR81411 to support a variety of applications. if the fsel pins are left floating, the xr 81411 will default (with internal pull-down resistors on the fsel inputs) to the frequency #1 output. output stages each of the XR81411s output interfaces can select between lvcmos, lvpecl or lvds. if selected for lvc- mos operation, the driver can operate up to 200mhz. if selected for lvpecl or lvds operation the driver can operate up to 800mhz. figure 16: XR81411 output stage configuration of universal clock for each of the stages - input, pll and output - the final configuration needs to be programmed by the factory. please contact the factory so that samples can be pro- grammed for your specific application requirements and sent to you for your validation before ordering. to see a list of configuration options available for the XR81411 please send your request to commtechsupport@exar.com . table 1: output frequency selection fsel[1:0] output frequency (mhz) 00 frequency #1 01 frequency #2 10 frequency #3 11 frequency #4 zz frequency #1 out? q q output stage lvcmos lvpecl lvds control
? 2014 exar corporation XR81411 13 / 15 exar.com/XR81411 rev 1a mechanical dimensions 45-pin lga
? 2014 exar corporation XR81411 14 / 15 exar.com/XR81411 rev 1a
? 2014 exar corporation XR81411 15 / 15 exar.com/XR81411 rev 1a for further assistance: email: commtechsupport@exar.com exar technical documentation: http://www.exar.com/techdoc/ exar corporation headquarters and sales offices 48720 kato road tel: +1 (510) 668-7000 fremont, ca 95438 - usa fax: +1 (510) 668-7001 notice exar corporation reserves the right to make changes to the produc ts contained in this publication in order to improve design, p erformance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no re sponsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its product s in life support applications where the failure or malfunctio n of the product can reasonably be expected to cause failure of the life support system or to significantly af fect its safety or effectiveness. products are not authorized fo r use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user as sumes all such risks; (c) potential liability of exar cor- poration is adequately protected under the circumstances. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. ordering information note: * all devices must be factory programmed to the customers c onfiguration for use. contact factory for programming options at commtechsupport@exar.com. revision history part number package green operating temperature range packaging marking XR81411-f * 45-pin lga yes -40c to +85c tray XR81411 XR81411tr-f * 45-pin lga yes -40c to +85c tape and reel XR81411 XR81411evb eval board n/a n/a n/a n/a revision date description 1a november 2014 initial release.

▲Up To Search▲

Price & Availability of XR81411

	To Download XR81411 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .